PHLEGM v8 / Checkpoint 52 / SNES SPC700 indexed loads and loop/stack operations

Evidence: five ActRaiser core dumps taken on 2026-10-10 at 10:01 Phoenix time.
All five: 739 SPC700 retired instructions, 2458 cycles, PC=$09C4,
F6 at $09C3 (MOV A,!abs+Y) unimplemented. Main CPU still polling
PC=$9A63, PPU INIDISP=$80; no display image yet.

Added 60 runtime-defined SPC700 instruction programs to .phlegm;
new native library operations are generic numeric VM primitives only:
- ADD16: wrap full 16-bit effective addresses without changing PSW;
- PUSH/POP: generic 8-bit stack to the $0100 page;
- BNZ: branch on scratch/register not zero, without PSW changes;
- ASL/LSR/ROL/ROR 8-bit shift/rotate plus C/N/Z;
- ADC/SBC 8-bit ALU with C/H/V/N/Z flags.

SPC700 instructions enabled: indexed absolute/direct-page MOV/AND/OR/EOR/CMP,
PUSH/POP, DBNZ, CBNE, shifts, accumulator arithmetic, DP INC/DEC, etc.
SPC700 instruction selection remains entirely in .phlegm and compiles
on machine loads; unsupported opcodes continue to stop explicitly.
No change to main CPU opcode model or session binary serialization.

Validation: opcode coverage, VM program syntax, byte/flag/cycle behavior
of selected programs statically and with isolated Python model tests
(external private testing only; no Python shipped). ZIP integrity verified.
Native FreeBASIC compilation and hands-on ActRaiser boot remain unverified.
